The present invention relates to the electrical, electronic, and computer arts, and, more particularly, to interconnection structures and methods for fabricating same.
In standard integrated circuit (IC) fabrication technology, interconnects serve as pathways of the IC, connecting various elements or functional blocks of the IC into a functioning whole and to the outside world. An IC typically has multiple interconnect levels (or metal layers) which vary in number depending on the complexity of the device and/or the fabrication technology employed, among other factors. These interconnect levels are formed in distinct vertical planes separated from one another by insulating layers formed therebetween. Elements in two different interconnect levels are electrically connected using vias, which are essentially holes etched through the IC and filled or lined with conductive material to form a conductive plug.
As IC feature size and spacing continually shrink, it becomes increasingly more challenging to align the vias with their underlying metal wires being connected. Such misalignment results in an overlay error, which can cause an unwanted electrical short between the via and a corresponding lower metal wire. Alternatively, this misalignment of the interconnect via may go undiscovered during wafer testing, only to manifest itself subsequently as time-dependent dielectric breakdown in the IC device, thereby resulting in premature failure of the device or severe performance degradation.